1. Field
Example embodiments relate to a semiconductor device, and more particularly, to a voltage generator that can generate a more accurate target voltage level in a semiconductor memory.
2. Description of the Related Art
Flash memories are nonvolatile storage devices that can electrically erase or rewrite data. Flash memories consume less power than storage devices based on magnetic disk memories, and have a fast access time comparable to hard disks.
Flash memories are classified into NOR flash memories and NAND flash memories according to a connection structure of cells and bit lines. In NOR flash memories, two or more cell transistors are connected in parallel to one bit line. NOR flash memories store data using channel hot electron injection, and erase data using Fowler-Nordheim (F-N) tunneling. In NAND flash memories, two or more cell transistors are connected in series to one bit line. NAND flash memories store and erase data using F-N tunneling. Generally, NOR flash memories are disadvantageous to high density of integration because of their high current consumption, but advantageous to high speed operation. NAND flash memories are advantageous to high density of integration because their lower cell current relative to NOR flash memories.
FIG. 1 is a cross-sectional view of a unit cell of a flash memory.
Referring to FIG. 1, a flash memory stores data in an array of floating gate transistors, called cells. The flash memory includes a p-type semiconductor substrate 11 doped with boron ions or the like. An n-type source region 12 and an n-type drain region 13 may be formed in the substrate 11 by doping phosphorus, arsenic, or antimony into the substrate 11. A floating gate 14 may be formed over the substrate 11 or may be isolated from the substrate 11. A control gate 15 may be formed over the floating gate 14 or may be isolated from the floating gate 14. Since the floating gate 14 is completely isolated from others, charges stored in the floating gate 14 are trapped and data can be retained in the floating gate 14 without power consumption.
FIG. 2A is a circuit diagram of a memory cell structure in a conventional NAND flash memory.
Referring to FIG. 2A, the conventional NAND flash memory includes a plurality of word lines WL11 through WL14 and a plurality of memory cells M11 through M14. The memory cells M11 through M14 and select transistors ST1 and ST2 are arranged in a string structure and are connected in series between a bit line BL and a ground voltage terminal VSS. Since the NAND flash memory uses a small cell current, all memory cells connected to one word line are programmed by a one-time program operation.
FIG. 2B is a circuit diagram of a memory cell structure in a conventional NOR flash memory.
Referring to FIG. 2B, the conventional NOR flash memory includes a plurality of memory cells M21 through M26 connected between bit lines BL1 and BL2 and a source select line CSL. Since the NOR flash memory uses a large cell current, a predetermined number of memory cells are programmed by a one-time program operation.
FIGS. 3A and 3C are graphs, respectively, illustrating cell threshold voltages of stored data when the memory cells of the flash memory are single-level cells (SLCs), and FIGS. 3B and 3D are graphs, respectively, illustrating cell threshold voltages of stored data when the memory cells of the flash memory are multi-level cells (MLCs).
Referring to FIGS. 3A and 3C, the SLC stores 1-bit data with two different threshold voltages programmed in the memory cell. For example, in the case of FIG. 3A, data stored in the memory cell is logic “1” when the threshold voltage programmed in the memory cell is in the range between 1 V and 3 V, and data stored in the memory cell is logic “0” when the threshold voltage programmed in the memory cell is in the range between 5 V and 7 V. A voltage distribution of an SLC NOR flash memory is illustrated in FIG. 3A, and a voltage distribution of an SLC NAND flash memory is illustrated in FIG. 3C.
Referring to FIGS. 3B and 3D, the MLC stores 2-bit data with four different threshold voltages programmed in the memory cell. For example, in the case of FIG. 3B, data stored in the memory cell is logic “11” when the threshold voltage programmed in the memory cell is in the range between 1 V and 3 V, and data stored in the memory cell is logic “10” when the threshold voltage programmed in the memory cell is in the range between 3.8 V and 4.2 V. Data stored in the memory cell is logic “01” when the threshold voltage programmed in the memory cell is in the range between 4.9 V and 5.4 V, and data stored in the memory cell is logic “01” when the threshold voltage programmed in the memory cell is in the range between 6.5 V and 7.0 V. A voltage distribution of an MLC NOR flash memory is illustrated in FIG. 3B, and a voltage distribution of an MLC NAND flash memory is illustrated in FIG. 3D.
In the SLC or MLC flash memories, data stored in the memory cell are distinguished by a cell current difference in a read operation. Since the operations and types of the flash memories described above are well known to those of ordinary skill in the art, detailed description thereof will be omitted.
As described above, the flash memories use various high voltage levels. To this end, the conventional flash memories use a high voltage generator to generate high voltages of various levels. However, since a voltage margin between data in MLC flash memories is reduced, it is important to generate an accurate high voltage level.
Furthermore, when a program operation is performed using an Increment Step Plus Program (ISPP) scheme of the MLC flash memory, step voltages with a smaller margin are required and thus parasitic resistances generated within the high voltage generator may effect an accuracy of the voltage generator.